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Performance analysis of 16x16,32x32,64x64 2-D mesh topologies for network on chip application of MIMO

Show simple item record Charanarur P. Rane, U.V. Gad, V.R. Kovendan, A.K.P. Sridharan, D. Gad, R.S. Naik, G.M. 2017-07-20T08:21:58Z 2017-07-20T08:21:58Z 2017
dc.identifier.citation WiSPNET-2017, technically sponsored by IEEE and IEEE ComSoc. Chennai-603110, India, 22-24 Mar 2017. 2017; 7pp. en_US
dc.description.abstract Network on Chip (NoC) is an up-coming worldview that adapts to the expanding many-sided quality and correspondence prerequisite of future System on Chip (SoC). Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the Mesh topology for 4X4 and 8X8 ,16x16,32x32,64x64 nodes for varying packets size (0.1 and 16000Kbytes), queue size(5-200), link bandwidth(10-200Mbps), link propagation delay(10-200ms), over CBR(5 and 10Mbps) and FTP applications. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low(0.512Kbytes) and high load(64Kbytes) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to accomplish ideal execution for respective applications of future wireless communications systems is to provide sensor data transmission high-data-rate,quality of service (QoS),low cost,speed of wireless access .Multiple-input multiple-output (MIMO) wireless technology meet these demands spectral efficiency, and improved link reliability. en_US
dc.subject Electronics en_US
dc.title Performance analysis of 16x16,32x32,64x64 2-D mesh topologies for network on chip application of MIMO en_US
dc.type Conference article en_US

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