Network on chip performance analysis over 2-D and 3D mesh topologies for CBR & FTP applications

Abstract

Network on Chip (NoC) is an approach to designing the communication subsystem between IP cores in a System on a Chip (SoC).Numerous topologies with various capacities have been proposed for NoCs, various topologies and parameters are chosen based on different NoC applications. In this paper, we have modeled the 2DMesh topology for 16X16,2D Torus 16x16 and 3D 18x18 nodes for varying packets size (0.1 and 16000Kbytes), queue size(5-200), link bandwidth(10-200Mbps), link propagation delay(10-200ms), over CBR(5 and 10Mbps) and FTP applications. This paper presents the design of a scalable packet based router allowing data transfer and managing dynamically several communications in parallel. The performance of throughput and propagation delay of packets from given source node to destination node is studied for low(0.512Kbytes) and high load(64Kbytes) applications. Point by point similar investigation of the reproduction brings about terms of latency and throughput are displayed. The outcomes can be utilized as a rule for NoC architects to settle on fitting decisions keeping in mind the end goal to accomplish ideal execution for respective applications of future wireless communications systems is to provide sensor data transmission high-data-rate,quality of service (QoS),low cost,speed of wireless access.