IR @ Goa University

Building embedded systems using soft IP cores

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dc.contributor.author Parab, J.S.
dc.contributor.author Gad, R.S.
dc.contributor.author Naik, G.M.
dc.date.accessioned 2017-11-15T06:25:45Z
dc.date.available 2017-11-15T06:25:45Z
dc.date.issued 2018
dc.identifier.citation Hands-on Experience with Altera FPGA Development Boards by Jivan S. Parab; Rajendra S. Gad; G.M. Naik. Springer (India) Pvt. Ltd. 2018; 73-78. en_US
dc.identifier.uri https://link.springer.com/chapter/10.1007/978-81-322-3769-3_4
dc.identifier.uri http://irgu.unigoa.ac.in/drs/handle/unigoa/5033
dc.description.abstract This chapter makes reader aware of embedded soft core processors, their concepts, comparisons of various soft cores from various FPGA manufactures, etc. Here, we have emphasized on Altera Nios II soft core processor. The soft core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II basic functionality by adding a predefined memory management unit or defining custom instructions and custom peripherals. Altera's Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. Design development flow of Nios II System is also depicted in pictorial form which is self-explanatory for the reader. en_US
dc.publisher Springer en_US
dc.subject Electronics en_US
dc.title Building embedded systems using soft IP cores en_US
dc.type Book chapter en_US


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