dc.contributor.author |
Parab, J.S. |
|
dc.contributor.author |
Gad, R.S. |
|
dc.contributor.author |
Naik, G.M. |
|
dc.date.accessioned |
2017-11-15T06:25:45Z |
|
dc.date.available |
2017-11-15T06:25:45Z |
|
dc.date.issued |
2018 |
|
dc.identifier.citation |
Hands-on Experience with Altera FPGA Development Boards by Jivan S. Parab; Rajendra S. Gad; G.M. Naik. Springer (India) Pvt. Ltd. 2018; 79-101. |
en_US |
dc.identifier.uri |
https://link.springer.com/chapter/10.1007/978-81-322-3769-3_5 |
|
dc.identifier.uri |
http://irgu.unigoa.ac.in/drs/handle/unigoa/5034 |
|
dc.description.abstract |
This chapter gives an introduction to Altera's SOPC Builder, which is used for the implementation of system that uses the Nios II processor on an Altera FPGA device. The system development flow is illustrated by giving step-by-step instructions for using the System-On-a-Programmable-Chip (SOPC) Builder in conjunction with the Quartus II software (Version 7.2) to implement a desired system. The final step in the development process is to configure the circuit designed in a FPGA device and running a desired application program in C/C++ using Nios II IDE. |
en_US |
dc.publisher |
Springer |
en_US |
dc.subject |
Electronics |
en_US |
dc.title |
How to build first Nios II system |
en_US |
dc.type |
Book chapter |
en_US |