Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC)

Abstract

In symmetric 3-D chip stacking, TSVs plays an important role and provides denser and fine pitches. The number of vertical links in 3-D mesh NoC topology is equal to 2 (N - (sup(3) square root N sup(2))), where N is the number of network nodes. The TSVs use pads for establishing a connection between the layers, which could generate the misalignment issue due to chip warpage, thermal stress, and TSVs cross-coupling, which notifies a maximum permitted density of TSVs Keep-Out Zone. The study has discussed the analytical model of the seven-port router to express an average number of packets at equilibrium conditions for the physical and virtual channel and demonstrated the performance model. The latency objective function is deduced over reduced global interconnect and algorithm proposed for adaptive XYZ routing, in support of TSV placement scheme. Later the analytical model is emulated for practical significance.