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Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC)

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dc.contributor.author Panem, C.
dc.contributor.author Gad, R.S.
dc.contributor.author Kaushik, B.
dc.date.accessioned 2021-09-06T07:02:31Z
dc.date.available 2021-09-06T07:02:31Z
dc.date.issued 2021
dc.identifier.citation Microelectronics Journal. 116; 2021; ArticleID_105231. en_US
dc.identifier.uri https://doi.org/10.1016/j.mejo.2021.105231
dc.identifier.uri http://irgu.unigoa.ac.in/drs/handle/unigoa/6546
dc.description.abstract In symmetric 3-D chip stacking, TSVs plays an important role and provides denser and fine pitches. The number of vertical links in 3-D mesh NoC topology is equal to 2 (N - (sup(3) square root N sup(2))), where N is the number of network nodes. The TSVs use pads for establishing a connection between the layers, which could generate the misalignment issue due to chip warpage, thermal stress, and TSVs cross-coupling, which notifies a maximum permitted density of TSVs Keep-Out Zone. The study has discussed the analytical model of the seven-port router to express an average number of packets at equilibrium conditions for the physical and virtual channel and demonstrated the performance model. The latency objective function is deduced over reduced global interconnect and algorithm proposed for adaptive XYZ routing, in support of TSV placement scheme. Later the analytical model is emulated for practical significance. en_US
dc.publisher Elsevier en_US
dc.subject Electronics en_US
dc.title Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC) en_US
dc.type Journal article en_US
dc.identifier.impf y


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