Configurable CRC error detection model for performance analysis of polynomial: Case study for the 32-Bits ethernet protocol

Abstract

Almost every form of digital information exchange can introduce communication errors. In order to overcome the inherent inaccuracy of information transmission, a few methods for error detection and correction have been developed. Cyclic Redundancy check Codes (CRCs) are used in embedded networks for effective error detection. Paper discusses the development of the simulation model for the configurable CRC-polynomials performance analysis over Binary Symmetric Channels (BSCs). This paper presents a novel model which can be used to investigate several classes of CRC polynomials codes with 'n' parity bits varying from '1' to '64'. It also discuss the hardware implementation on Altera's FPGA Stratix II GX device 'EP2SGX90FF1508C3' for CRC-32 'IEEE-802' and suggest the indirect methodology of CRC-performance using Packet Error Rate (PER) parameter using Altera TSE MegaCore function that supports 10/100/1000 Mbps Ethernet over 1000Base-LX physical media. It is proposed to search good CRC codes of 32, 40 and 64 bit and studying performance for maximum payload over Ethernet protocol.